;	Copyright (c) 2002 ALi Corp. 
;		ALi M5603C Pc-Camera inital setting
; 	Format
;		R 	register	data
;		I	device		address		data	
;  		P	register	and_data	compare_data	
;		O	register	Or_data				
;		A	register	And_data
;		C	register	min(0%)		max(100%)
;
;	xbFwMode0: 7: 
;		   6:
;		   5: ae reset
;		   4: awb reset
;		   3:
;		   2: snapshot enable
;		   1: ae enable
;		   0: awb enable
;		
;	Sensor: OV7640
;	Version: 0.005


[BEGIN]


[N_VGA]

[N_QVGA]



[N_CIF]

[N_QCIF]
[_R_VGA]

R	xbImageSize		0x01	;
R	xbDebug			0x02	;
O	xbTestReg		0x10	; No HandShake

; VGA start
R	xbDMNCTL		0x00    ; bit3: decimation
R	xbDMCTRL		0x04	; 0x8017
R	xbDWNVECV		0xFF	; 0x801C
R       xbDWNVECH		0xFF	; 0x801D

R	xbLineStart0		0x04	; 0x8001
R	xbLineEnd0		0x03	; 0x8002
R	xbPixStart0		0x28	; 0x8003
R	xbPixEnd0		0x27	; 0x8004	

R	xbImgWinMSBL		0x04	; 0x8005
R	xbImgWinMSBP		0x05	; 0x8006
R	xbLineLength		0xA0	; 0x8007 this number should be equal the input image size/8





R	xbLbufClkControl	0x0C	; Clock enable, 60M, division Disable
R	xbLbufClkDivision	0x00	; 
R	xbCprClkControl		0x0C	; Clock enable, 60M, division disable	
R	xbCprClkDivision	0x00	;
R	xbDSPCTRL		0x20	; Reset DSP
R	xbEPAFCTR		0x10	; Reset EPA Fifo
R	xbDSPCTRL		0x60	; Reset Image, Stop Image
R	xbDSPCTRL		0x48	; Stop Image
O	xbJpegControl		0x02	; Reset JPEG
A	xbJpegControl		0xEE	; Jpeg Disable, Jpeg Start = 0

;R	xbLbufClkControl	0xC0	; Clock enable, 60M, division Disable
;R	xbLbufClkDivision	0x00	; 
R	xbCprClkControl		0x08	; Clock enable, 60M, division disable	
R	xbCprClkDivision	0x00	;
R	xbLbufClkControl	0x00	; Clock enable, 60M, division Disable
R	xbLbufClkDivision	0x00	; 
R	xbDctClkControl		0x00	;Clock enable, 60M, division disable	
R	xbDctClkDivision	0x00	;
R	xbEcClkControl		0x00	;Clock enable, 80M, division disable	
R	xbEcClkDivision		0x00	;
[R_VGA_]
R	xbImageSize		0x01	;
R	xbDebug			0x02	;
O	xbTestReg		0x10	; No HandShake

; VGA start
;R	xbDMNCTL		0x00    ; bit3: decimation
;R	xbDMCTRL		0x04	; 0x8017
;R	xbDWNVECV		0xFF	; 0x801C
;R   xbDWNVECH		0xFF	; 0x801D
;
;R	xbLineStart0	0x00	; 0x8001
;R	xbLineEnd0		0xDF	; 0x8002
;R	xbPixStart0		0x00	; 0x8003
;R	xbPixEnd0		0x7F	; 0x8004	
;
;R	xbImgWinMSBL		0x01	; 0x8005
;R	xbImgWinMSBP		0x02	; 0x8006
;R	xbLineLength		0x50	; 0x8007 this number should be equal the input image size/8




		
R	xbBKNUMH0		0x9F	; 0x8008;
R	xbBKNUMV0		0x7F	; 0x8009;
R	xbBKNUMMSB		0x00	; 0x800a;
R	xbHBlockNoJp		0xA0	; 0x8160
R	xbVBlockNoJp		0x80	; 0x8161

R	xbMETWIN_MSB    	0x00	; 0x8034

;VGA end

R	xbLbufClkControl	0x0C	; Clock enable, 60M, division Disable
R	xbLbufClkDivision	0x00	; 
R	xbCprClkControl		0x0C	; Clock enable, 60M, division disable	
R	xbCprClkDivision	0x00	;
R	xbDSPCTRL		0x20	; Reset DSP
R	xbEPAFCTR		0x10	; Reset EPA Fifo
R	xbDSPCTRL		0x60	; Reset Image, Stop Image
R	xbDSPCTRL		0x48	; Stop Image
O	xbJpegControl		0x02	; Reset JPEG
A	xbJpegControl		0xEE	; Jpeg Disable, Jpeg Start = 0

;R	xbLbufClkControl	0xC0	; Clock enable, 60M, division Disable
;R	xbLbufClkDivision	0x00	; 
R	xbCprClkControl		0x09	; Clock enable, 60M, division disable	
R	xbCprClkDivision	0x00	;
R	xbLbufClkControl	0x00	; Clock enable, 60M, division Disable
R	xbLbufClkDivision	0x00	; 
R	xbDctClkControl		0x00	;Clock enable, 60M, division disable	
R	xbDctClkDivision	0x00	;
R	xbEcClkControl		0x00	;Clock enable, 80M, division disable	
R	xbEcClkDivision		0x00	;

;O	xbBBUF_EN		0x30	; 0x806A

;R	xbEPAFCTR		0x10	;
;R	xbEPAFCTR		0x00	;
[R_QVGA]

[R_CIF]

[R_QCIF]

[NJ4_VGA]

[NJ4_QVGA]
 
[NJ4_CIF]
 
[NJ4_QCIF]


[NJ2_VGA]


[NJ2_QVGA]
 
[NJ2_CIF]

 
[NJ2_QCIF]



[CONTRAST0]


[CONTRAST10]


[CONTRAST20]

[CONTRAST30]
	

[CONTRAST40]


[CONTRAST50]

[CONTRAST60]


[CONTRAST70]
[CONTRAST80]

[CONTRAST90]

[CONTRAST100]

	

[SATURATION0]



[SATURATION10]



[SATURATION20]



[SATURATION30]

	

[SATURATION40]


[SATURATION50]


[SATURATION60]


[SATURATION70]

[SATURATION80]

[SATURATION90]


[SATURATION100]


[BRIGHTNESS0]


[BRIGHTNESS10]


[BRIGHTNESS20]


[BRIGHTNESS30]


[BRIGHTNESS40]

[BRIGHTNESS50]



[BRIGHTNESS60]



[BRIGHTNESS70]



[BRIGHTNESS80]


[BRIGHTNESS90]

[BRIGHTNESS100]


[SHARPNESS0]


[SHARPNESS10]


[SHARPNESS20]


[SHARPNESS30]


[SHARPNESS40]


[SHARPNESS50]


[SHARPNESS60]

[SHARPNESS70]


[SHARPNESS80]

[SHARPNESS90]

[SHARPNESS100]
	
[VGA_FLICKER_DISABLE_HS]

[VGA_FLICKER_60HZ_HS]


[VGA_FLICKER_50HZ_HS]


[VGA_FLICKER_DISABLE_FS]


[VGA_FLICKER_60HZ_FS]

[VGA_FLICKER_50HZ_FS]

[CIF_FLICKER_DISABLE_HS]

[CIF_FLICKER_60HZ_HS]



[CIF_FLICKER_50HZ_HS]



[CIF_FLICKER_DISABLE_FS]




[CIF_FLICKER_60HZ_FS]



[CIF_FLICKER_50HZ_FS]
[AWB]


[TUNGSTEN]	
[FLUORESCENT]

[DAYLIGHT]

[DSP_INIT]
R	xbDebug			0xFF	;
O	xbFwVersionMSB		0x00	;
O	xbFwVersionLSB		0x00	;
R	xbFwMode0		0x00	; Disable all
R	xbGPIODIRH		0xFF	;
R       xbGPIODATAH             0x40    ;
D       0xFF
D       0xFF
D       0xFF
O	xbGPIODATAH		0x40	;

R	xbMISC_IO_DAT		0x00	;
R	xbSenClkControl		0x0D	;Clock enable, 48M, division enable	
R	xbSenClkDivision	0x01	;80M/3
R	xbLbufClkControl	0x0C	;Clock enable, 80M, division disable	
R	xbLbufClkDivision	0x00	;
R	xbCprClkControl		0x0C	;Clock enable, 60M, division disable	
R	xbCprClkDivision	0x00	;
R	xbDctClkControl		0x0C	;Clock enable, 60M, division disable	
R	xbDctClkDivision	0x00	;
R	xbEcClkControl		0x0C	;Clock enable, 80M, division disable	
R	xbEcClkDivision		0x00	;
R	xbMcuClkControl		0x09	;Clock enable, 48M, division disable	
R	xbMcuClkDivision	0x02	;
	
R	xbDSPCTRL		0x60	;

;	==========
;	Image Capture Window Coordination
;	==========
R	xbLineStart0		0x14	; 0x8001
R	xbLineEnd0		0xF3	; 0x8002
R	xbPixStart0		0x15	; 0x8003
R	xbPixEnd0		0x94	; 0x8004
	
R	xbImgWinMSBL		0x01	; 0x8005
R	xbImgWinMSBP		0x02	; 0x8006
R	xbLineLength		0x50	; 0x8007		
	
;	==========
;	Block Number
;	==========

R	xbBKNUMH0		0x4F	; 0x8008
R	xbBKNUMV0		0x3B	; 0x8009
R	xbBKNUMMSB		0x00	; 0x800a
	
;	==========
;	Optical Black Control
;	==========
R	xbBLACKCTL		0x00	; 0x800B
R	xbOBSTART_MSB		0x00	; 
R	xbBlackLineStart	0x00	; 0x800D
R	xbBlackStart		0x00	; 0x800E
R	xbBlackClampLSB		0x00	; 0x800F
R	xbBlackClampMSB		0x00	; 0x8010
R	xbSMETCTRL		0x17	; 0x802A


R	xbCOF_YTURNPT		0xFF	; 0x8013
R	xbCOF_YTURNPT		0xF0	; 0x8013
R	xbCOF_YTURNPT		0xE0	; 0x8013
R	xbCOF_YTURNPT		0xD0	; 0x8013
R	xbCOF_YTURNPT		0xC0	; 0x8013
R	xbCOF_YTURNPT		0xB0	; 0x8013
R	xbCOF_YTURNPT		0xA0	; 0x8013
R	xbCOF_YTURNPT		0x90	; 0x8013
R	xbCOF_YTURNPT		0x80	; 0x8013
R	xbCOF_YTURNPT		0x70	; 0x8013
R	xbCOF_YTURNPT		0x60	; 0x8013
R	xbCOF_YTURNPT		0x50	; 0x8013
R	xbCOF_YTURNPT		0x40	; 0x8013
R	xbCOF_YTURNPT		0x30	; 0x8013
R	xbCOF_YTURNPT		0x20	; 0x8013
R	xbCOF_YTURNPT		0x10	; 0x8013
R	xbCOF_YTURNPT		0x00	; 0x8013

R	xbPRC_SHT		0x00	; 0x8069		


R	xbDMCTRL		0x04	; 0x8017
R	xbDMLOW			0x20	; 0x8018
R	xbDMHIGH		0x40	; 0x8019
R	xbDMHVDF		0xFF	; 0x801A
	
R	xbDMNCTL		0x00	; 0x801B	bit3: decimation
R	xbDWNVECV		0xFF	; 0x801C
R	xbDWNVECH		0xFF	; 0x801D

R	xbRDARK			0x30	; 0x801E
R	xbRLIGHT		0x00	; 0x801F
R	xbREDDTH		0x00	; 0x8020
R	xbREDLTH		0x00	; 0x8021
R	xbGDARK			0x30	; 0x8022
R	xbGLIGHT		0x00	; 0x8023
R	xbGREENDTH		0x00	; 0x8024
R	xbGREENLTH		0x00	; 0x8025
R	xbBDARK			0x30	; 0x8026
R	xbBLIGHT		0x00	; 0x8027
R	xbBLUEDTH		0x00	; 0x8028
R	xbBLUELTH		0x00	; 0x8029

R	xbSMETWIN_MSBL		0x00	; 0x802B
R	xbSMETWIN_MSBP		0x00	; 0x802C
R	xbSMET_SLINE		0x00	; 0x802D
R	xbSMET_ELINE		0x00	; 0x802E
R	xbSMET_SPIX		0x00	; 0x802F
R	xbSMET_EPIX		0x00	; 0x8030
                                  
R	xbSMET_BINHTH		0x00	; 0x8031
R	xbSMET_BINLTH		0x00	; 0x8032
R	xbMETCTRL		0x00	; 0x8033

R	xbMETWIN_MSB            0x00	; 0x8034
R	xbAEWIN_X1		0x19	; 0x8035
R	xbAEWIN_Y1		0x14	; 0x8036
R	xbAEWIN_X2		0x32	; 0x8037
R	xbAEWIN_Y2		0x28	; 0x8038
R	xbAWBWIN_X1		0x00	; 0x8039
R	xbAWBWIN_Y1		0x00	; 0x803A
R	xbAWBWIN_X2		0x13	; 0x803B
R	xbAWBWIN_Y2		0x0E	; 0x803C

R	xbYTH_H			0xF8	; 0x803D
R	xbYTH_L			0x00	; 0x803E
R	xbUTH_H			0xFF	; 0x803F
R	xbUTH_L			0x00	; 0x8040
R	xbVTH_H			0xFF	; 0x8041
R	xbVTH_L			0x00	; 0x8042
R	xbRGBTHR_H		0xFF	; 0x8043

;	==========
;	Color Matrix Coefficient
;	==========

R	xbPRC_SHT		0x00	; 0x8069                                                 
R	xbCOF_RY		0x26	; 299*128/1000  0x804D
R	xbCOF_GY		0x4B	; 587*128/1000  0x804E
R	xbCOF_BY		0x0F	; 114*128/1000  0x804F

R	xbCOF_ROFFSET		0x00	; 0x8050
R	xbCOF_GOFFSET		0x00	; 0x8051
R	xbCOF_BOFFSET		0x00	; 0x8052
R	xbCOF_YOFFSET		0x00	; 0x8053
R	xbCOF_AWB_RGAIN		0x40	; 0x8054
R	xbCOF_AWB_GGAIN		0x40	; 0x8055
R	xbCOF_AWB_BGAIN		0x40	; 0x8056
 
;	==========
;	Edge Enhancement
;	==========

R	xbCOF_EDGE_HTH		0xC0	; 0x8057
R	xbCOF_EDGE_LTH		0x20	; 0x8058
R	xbCOF_EDGE_GAIN		0x18	; 0x8059
R	xbCOF_HF_GAIN		0x10	; 0x805A


R	xbCOF_RU		0xEA	; 0x805C
R	xbCOF_GU		0xD6	; 0x805D
R	xbCOF_BU		0x40	; 0x805E
R	xbCOF_RV		0x40	; 0x805F
R	xbCOF_GV		0xCA	; 0x8060
R	xbCOF_BV		0xF6	; 0x8061

R	xbCOF_TD_YOFFSET	0x00	; 0x8062
R	xbCOF_TD_UOFFSET	0x00	; 0x8063
R	xbCOF_TD_VOFFSET	0x00	; 0x8064

R	xbCOF_AE_YGAIN		0x40	; 0x8065
R	xbCOF_AE_UGAIN		0x40	; 0x8066
R	xbCOF_AE_VGAIN		0x40	; 0x8067

R	xbOBSFRAME		0x20	; 0x8156

R	xbHBlockNoJp		0x50	; 0x8160
R	xbVBlockNoJp		0x3C	; 0x8161
R	xbJpegControl		0x01	; 0x8162
R	xbQTableIndex		0x40	; 0x8163
R	xbJpegControl		0x02	; 0x8162 
R	xbJpegControl		0x01	; 0x8162
                     		
R	xbJpegControl		0x19	; 4:2:2 0x8162

R	xbRGAMA			0xF8	; 0x8011
R	xbRGAMA			0xE8	; 0x8011
R	xbRGAMA			0xD8	; 0x8011
R	xbRGAMA			0xC8	; 0x8011
R	xbRGAMA			0xB8	; 0x8011
R	xbRGAMA			0xA8	; 0x8011
R	xbRGAMA			0x98	; 0x8011
R	xbRGAMA			0x88	; 0x8011
R	xbRGAMA			0x78	; 0x8011
R	xbRGAMA			0x68	; 0x8011
R	xbRGAMA			0x58	; 0x8011
R	xbRGAMA			0x48	; 0x8011
R	xbRGAMA			0x38	; 0x8011
R	xbRGAMA			0x28	; 0x8011
R	xbRGAMA			0x18	; 0x8011
R	xbRGAMA			0x08	; 0x8011
R	xbRGAMA			0xFF	; 0x8011
R	xbRGAMA			0xF0	; 0x8011
R	xbRGAMA			0xE0	; 0x8011
R	xbRGAMA			0xD0	; 0x8011
R	xbRGAMA			0xC0	; 0x8011
R	xbRGAMA			0xB0	; 0x8011
R	xbRGAMA			0xA0	; 0x8011
R	xbRGAMA			0x90	; 0x8011
R	xbRGAMA			0x80	; 0x8011
R	xbRGAMA			0x70	; 0x8011
R	xbRGAMA			0x60	; 0x8011
R	xbRGAMA			0x50	; 0x8011
R	xbRGAMA			0x40	; 0x8011
R	xbRGAMA			0x30	; 0x8011
R	xbRGAMA			0x20	; 0x8011
R	xbRGAMA			0x10	; 0x8011
R	xbRGAMA			0x00	; 0x8011


R	xbGGAMA			0xF8	; 0x8011
R	xbGGAMA			0xE8	; 0x8011
R	xbGGAMA			0xD8	; 0x8011
R	xbGGAMA			0xC8	; 0x8011
R	xbGGAMA			0xB8	; 0x8011
R	xbGGAMA			0xA8	; 0x8011
R	xbGGAMA			0x98	; 0x8011
R	xbGGAMA			0x88	; 0x8011
R	xbGGAMA			0x78	; 0x8011
R	xbGGAMA			0x68	; 0x8011
R	xbGGAMA			0x58	; 0x8011
R	xbGGAMA			0x48	; 0x8011
R	xbGGAMA			0x38	; 0x8011
R	xbGGAMA			0x28	; 0x8011
R	xbGGAMA			0x18	; 0x8011
R	xbGGAMA			0x08	; 0x8011
R	xbGGAMA			0xFF	; 0x8011
R	xbGGAMA			0xF0	; 0x8011
R	xbGGAMA			0xE0	; 0x8011
R	xbGGAMA			0xD0	; 0x8011
R	xbGGAMA			0xC0	; 0x8011
R	xbGGAMA			0xB0	; 0x8011
R	xbGGAMA			0xA0	; 0x8011
R	xbGGAMA			0x90	; 0x8011
R	xbGGAMA			0x80	; 0x8011
R	xbGGAMA			0x70	; 0x8011
R	xbGGAMA			0x60	; 0x8011
R	xbGGAMA			0x50	; 0x8011
R	xbGGAMA			0x40	; 0x8011
R	xbGGAMA			0x30	; 0x8011
R	xbGGAMA			0x20	; 0x8011
R	xbGGAMA			0x10	; 0x8011
R	xbGGAMA			0x00	; 0x8011


R	xbBGAMA			0xF8	; 0x8011
R	xbBGAMA			0xE8	; 0x8011
R	xbBGAMA			0xD8	; 0x8011
R	xbBGAMA			0xC8	; 0x8011
R	xbBGAMA			0xB8	; 0x8011
R	xbBGAMA			0xA8	; 0x8011
R	xbBGAMA			0x98	; 0x8011
R	xbBGAMA			0x88	; 0x8011
R	xbBGAMA			0x78	; 0x8011
R	xbBGAMA			0x68	; 0x8011
R	xbBGAMA			0x58	; 0x8011
R	xbBGAMA			0x48	; 0x8011
R	xbBGAMA			0x38	; 0x8011
R	xbBGAMA			0x28	; 0x8011
R	xbBGAMA			0x18	; 0x8011
R	xbBGAMA			0x08	; 0x8011
R	xbBGAMA			0xFF	; 0x8011
R	xbBGAMA			0xF0	; 0x8011
R	xbBGAMA			0xE0	; 0x8011
R	xbBGAMA			0xD0	; 0x8011
R	xbBGAMA			0xC0	; 0x8011
R	xbBGAMA			0xB0	; 0x8011
R	xbBGAMA			0xA0	; 0x8011
R	xbBGAMA			0x90	; 0x8011
R	xbBGAMA			0x80	; 0x8011
R	xbBGAMA			0x70	; 0x8011
R	xbBGAMA			0x60	; 0x8011
R	xbBGAMA			0x50	; 0x8011
R	xbBGAMA			0x40	; 0x8011
R	xbBGAMA			0x30	; 0x8011
R	xbBGAMA			0x20	; 0x8011
R	xbBGAMA			0x10	; 0x8011
R	xbBGAMA			0x00	; 0x8011

R	xbCOF_RR		0x20	; 0x8044
R	xbCOF_GR		0x00	; 0x8045
R	xbCOF_BR		0x00	; 0x8046		
R	xbCOF_RG		0x00	; 0x8047
R	xbCOF_GG		0x20	; 0x8048
R	xbCOF_BG		0x00	; 0x8049
R	xbCOF_RB		0x00	; 0x804A
R	xbCOF_GB		0x00	; 0x804B
R	xbCOF_BB		0x20	; 0x804C

R	xbSIF_RGain		0x40	; for compensate the ob-reduction
R	xbSIF_GGain		0x40	;
R	xbSIF_BGain		0x40	;

R	xbSensorType		0x10	; 0x8100
R	xbSIF_Reset		0x00	; 0x8101
O	xbTestReg		0x10	; No Handshake 0x8153
R	xbBBUF_EN		0x0F	; 0x806A

O	xbFwMode0		0x04	; Snapshot enable, bit0 Awb enable, bit1, Ae Enable
R	xbImageSize		0x01	;

;R 	xbSenClkControl		 0x09 	;
;R	xbSenClkDivision	 0x0A	;
O	xbMISC_IO_DIR		 0x06	;// i2c
A	xbMISC_IO_DAT		 0xF9	;
O	xbEPAFCTR 		 0x10	;
R	xbDSPCTRL		 0x60	;
A	xbBBUF_EN		 0xF0	; 0x806A
R	xbLbufClkControl	 0x00	;Clock enable, 80M, division disable	
R	xbLbufClkDivision	 0x00	;
R	xbCprClkControl		 0x00	;Clock enable, 60M, division disable	
R	xbCprClkDivision	 0x00	;
R	xbDctClkControl		 0x00	;Clock enable, 60M, division disable	
R	xbDctClkDivision	 0x00	;
R	xbEcClkControl		 0x00	;Clock enable, 80M, division disable	
R	xbEcClkDivision		 0x00	;
O	xbGPIODIRH		0x80	;
O	xbGPIODATAH		0x80	;

[LIB_INIT]

[AP_ON]


R	xbDebug			0xBB	;
O	xbFwVersionMSB		0x00	;
O	xbFwVersionLSB		0x00	;
R	xbMISC_IO_DAT		0x00	;
R	xbEPAFCTR		0x10	; Reset EPA Fifo
R	xbCprClkControl		0x0C	;Clock enable, 60M, division disable	
R	xbCprClkDivision	0x00	;
R	xbDSPCTRL		0x20	; Reset DSP
R	xbDSPCTRL		0x60	; Reset Image, Stop Image
R	xbDSPCTRL		0x48	; Stop Image
R	xbDctClkControl		0x0C	;Clock enable, 60M, division disable	
R	xbDctClkDivision	0x00	;
O	xbJpegControl		0x02	; Reset JPEG
A	xbJpegControl		0xEE	; Jpeg Disable, Jpeg Start = 0

R	xbSenClkControl		0x09	;Clock enable, 48M, division enable	
R	xbSenClkDivision	0x00	;48M/2
R	xbCprClkControl		0x0C	; Clock enable, 60M, division disable	
R	xbCprClkDivision	0x00	;
R	xbLbufClkControl	0x00	; Clock enable, 60M, division Disable
R	xbLbufClkDivision	0x00	; 
R	xbDctClkControl		0x00	;Clock enable, 60M, division disable	
R	xbDctClkDivision	0x00	;
R	xbEcClkControl		0x00	;Clock enable, 80M, division disable	
R	xbEcClkDivision		0x00	;





[AP_OFF]
R	xbSensorType		 0x10	; 0x8100
R	xbDebug			 0xEE	;
;R 	xbSenClkControl		 0x00 	;
;R	xbSenClkDivision	 0x00	;
O	xbMISC_IO_DIR		 0x06	;// i2c
A	xbMISC_IO_DAT		 0xF9	;
O	xbEPAFCTR 		 0x10	;
R	xbDSPCTRL		 0x60	;
A	xbBBUF_EN		 0xF0	; 0x806A
R	xbLbufClkControl	 0x00	;Clock enable, 80M, division disable	
R	xbLbufClkDivision	 0x00	;
R	xbCprClkControl		 0x00	;Clock enable, 60M, division disable	
R	xbCprClkDivision	 0x00	;
R	xbDctClkControl		 0x00	;Clock enable, 60M, division disable	
R	xbDctClkDivision	 0x00	;
R	xbEcClkControl		 0x00	;Clock enable, 80M, division disable	
R	xbEcClkDivision		 0x00	;
//A	xbGPIODATAH		 0x7F	;

[SUSPEND]

[RESUME]

[END]